timelogic.c File Reference

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include "constype.h"

Include dependency graph for timelogic.c:

Go to the source code of this file.

Functions
int	change_into_logic (SIGNALS *sp)
static int	same_inputs (INPUTS *ip, SIGNALS *sp, int clk_cycle)
static void	add_input_val (INPUTS *ip, SIGNALS *sp, int clk_cycle)
static void	add_delay (INPUTS *ip, int clk_cycle, TIME delta)
INPUTS *	compute_delays (SIGNALS *sp)
int	compute_holdsetup_time (SIGNALS *sp_good, SIGNALS *sp_bad, HOLDSETUP *holdset, int hold1setup0)

Function Documentation

static void add_delay ( INPUTS *  ip, int  clk_cycle, TIME  delta  )

static

Definition at line 106 of file timelogic.c.

{
 DELAYS *dp;

 dp = (DELAYS *) calloc(1, sizeof(DELAYS));
 dp->delta = delta;
 dp->clk_cycle=clk_cycle;
 dp->next=NULL;

 if(ip->last_delay!=NULL)
   ip->last_delay->next = dp;
 else
   ip->delay = dp;

 ip->last_delay=dp;
}   

static void add_input_val ( INPUTS *  ip, SIGNALS *  sp, int  clk_cycle  )

static

Definition at line 96 of file timelogic.c.

{
 int i;

 ip->input_val = (int*) calloc(sp->ins_num, sizeof(int));
 for(i=0; i<sp->ins_num; i++)
   ip->input_val[i] = sp->sig_log[sp->clk_num + i][clk_cycle].val;
}

int change_into_logic

(

SIGNALS *

sp

)

Definition at line 8 of file timelogic.c.

{
 PULSE *pclk, *psig, *tpsig;
 int clk_cycle, sig_nr;
 int tval, i;

 pclk=sp->sig_bgn[0];
 clk_cycle=0;
 while(pclk!=NULL)
   {
    clk_cycle++;
    pclk=pclk->next;
   }
 sp->clk_cycles_nr=clk_cycle+1;

 sp->clk_times=(TIME*)calloc(sp->clk_cycles_nr, sizeof(TIME));
 sp->sig_log= (LOGIC **)calloc(sp->signal_num, sizeof(LOGIC*));
 for(sig_nr=1; sig_nr<sp->signal_num; sig_nr++)
   sp->sig_log[sig_nr] = (LOGIC*)calloc(sp->clk_cycles_nr, sizeof(LOGIC));

 pclk=sp->sig_bgn[0];
 clk_cycle=1;
 while(pclk!=NULL)
   {
    sp->clk_times[clk_cycle++] = pclk->t;
    pclk=pclk->next;
   }

 for(sig_nr=1; sig_nr<sp->signal_num; sig_nr++)
  {
   psig=sp->sig_bgn[sig_nr];
   clk_cycle=0;

   while(psig!=NULL)
    {
     /* find the clock cycle the pulse belongs to */
     while(clk_cycle < sp->clk_cycles_nr-1)
      {
       if(sp->clk_times[clk_cycle+1] > psig->t)
         break;

       clk_cycle++;
      }

     /* counting the number of signal data pulses within clock cycle */
     tpsig=psig;
     tval = 0;
     while(tpsig!=NULL)
       if(sp->clk_times[clk_cycle+1] > tpsig->t)
        { tval ++; tpsig=tpsig->next; }
       else
         break;

     /* assign values to 
        the array of pulse positions within clock cycle */
     sp->sig_log[sig_nr][clk_cycle].val = tval;
     sp->sig_log[sig_nr][clk_cycle].delta = (TIME*)calloc(tval, sizeof(TIME));
     for(i=0; i<tval; i++, psig = psig->next)
       sp->sig_log[sig_nr][clk_cycle].delta[i] = 
       psig->t - sp->clk_times[clk_cycle]; 

     if(clk_cycle >= sp->clk_cycles_nr-1)
      break;

    }

   clk_cycle++;
   while(clk_cycle < sp->clk_cycles_nr-1)
     sp->sig_log[sig_nr][clk_cycle++].val=0;
  }
}

INPUTS* compute_delays

(

SIGNALS *

sp

)

Definition at line 125 of file timelogic.c.

{
 INPUTS *ip=NULL, *last_ip=NULL, *np;
 int k;

 for(k=1; k<sp->clk_cycles_nr; k++)
  {
   if(sp->sig_log[sp->signal_num-1][k].val==1)
    {
     np=ip;
     while(np!=NULL)
      {
       if(same_inputs(np, sp, k-1))
        {
         add_delay(np, k-1, sp->sig_log[sp->signal_num-1][k].delta[0]);
         goto next_cycle;
        }
       np=np->next;
      }

     np=(INPUTS *)calloc(1, sizeof(INPUTS));
     np->next=NULL;
     if(last_ip!=NULL)
       last_ip->next=np;
     else
       ip=np;

     last_ip=np;        
     add_input_val(np, sp, k-1);
     add_delay(np, k-1, sp->sig_log[sp->signal_num-1][k].delta[0]);        
    }
next_cycle: ;
  }
 return ip;
}

int compute_holdsetup_time	(	SIGNALS *	sp_good,
		SIGNALS *	sp_bad,
		HOLDSETUP *	holdset,
		int	hold1setup0
	)

Definition at line 164 of file timelogic.c.

{
 int i, ival;
 int clk_cycle;
 TIME delta, period;
 int done, delta_set;

 if((sp_good==NULL) || (sp_bad==NULL))
   return 0;
 if(sp_bad->signal_num!=sp_good->signal_num)
   return 0;
 if(sp_good->signal_num<3)
   return 0;
 if(sp_bad->clk_cycles_nr!=sp_good->clk_cycles_nr)
   return 0;
 if(sp_good->var_in_nr==0)
   return 0;

 done=0;

 for(i=1; i<sp_good->clk_cycles_nr; i++)
  {  
   if(sp_bad->sig_log[sp_bad->signal_num-1][i].val!=
      sp_good->sig_log[sp_good->signal_num-1][i].val)
    {
     delta_set=1;
     switch(hold1setup0)
      {
       case 1:  /* HOLD TIME */
               if(sp_good->sig_log[sp_good->var_in_nr][i-1].val>0) 
                delta=sp_good->sig_log[sp_good->var_in_nr][i-1].delta[0];
               else
               if(sp_good->sig_log[sp_good->var_in_nr][i-2].val>0)
                {
                 ival = sp_good->sig_log[sp_good->var_in_nr][i-2].val;
                 delta=sp_good->sig_log[sp_good->var_in_nr][i-2].delta[ival-1];
                 period = sp_good->clk_times[i-1]-sp_good->clk_times[i-2];
                 if(delta > period/2)
                  delta = -(period-delta);
                }
               else
                delta_set=0;
               break;

       case 0:  /* SETUP TIME */
               if(sp_good->sig_log[sp_good->var_in_nr][i-1].val>0) 
                {
                 ival = sp_good->sig_log[sp_good->var_in_nr][i-1].val;
                 period=sp_good->clk_times[i]-sp_good->clk_times[i-1];
                 delta=sp_good->sig_log[sp_good->var_in_nr][i-1].delta[ival-1];
                 delta=period-delta;
                }
               else
               if(sp_good->sig_log[sp_good->var_in_nr][i].val>0)
                {
                 delta=sp_good->sig_log[sp_good->var_in_nr][i].delta[0];
                 period = sp_good->clk_times[i+1]-sp_good->clk_times[i];
                 if(delta < period/2)
                  delta = -delta;
                 else
                  delta_set=0;
                }
               else
                 delta_set=0;

               if(!delta_set)
                if(sp_good->sig_log[sp_good->var_in_nr][i-2].val>0)
                 {
                  ival = sp_good->sig_log[sp_good->var_in_nr][i-2].val;
                  period=sp_good->clk_times[i-1]-sp_good->clk_times[i-2];
                  delta=sp_good->sig_log[sp_good->var_in_nr][i-2].delta[ival-1];
                  if(delta > period/2)
                    delta=period-delta;
                  else 
                    delta=-delta;
                  delta_set=1;                                   
                 }
      }
    
     if(delta_set)
      if((!done) || (delta > holdset->delta))
       {
        done=1;
        holdset->delta=delta;
        holdset->cycle=i-1;
        holdset->input=sp_good->var_in_nr;
       }
    }
  }

 return done;
}

static int same_inputs ( INPUTS *  ip, SIGNALS *  sp, int  clk_cycle  )

static

Definition at line 83 of file timelogic.c.

{
 int i;

 for(i=0; i<sp->ins_num; i++)
  {
   if(sp->sig_log[sp->clk_num + i][clk_cycle].val != ip->input_val[i])
     return 0;
  }
 return 1;
}