WRspice Circuit Simulator
IC Design Software for Unix/Linux and Windows
Whiteley Research Inc., 456 Flora Vista Avenue, Sunnyvale CA 94086 www.wrcad.com
WRspice Circuit Simulator
Whiteley Research Inc., www.wrcad.com

Click here to browse the on-line WRspice manual.
Click here to enter the on-line WRspice help system.

WRspice  is a powerful and flexible circuit simulation and analysis tool. WRspice is an extension of Jspice3, which was derived from Berkeley Spice3f4 and Spice2g.6. While WRspice is being developed to include new features, it will continue to support those capabilities and modes which remain in extensive use with the Spice2 and Spice3 programs.

Unlike the Jspice3 program, WRspice makes extensive use of input graphics and the point and click metaphor for program control. About a dozen different control panels are available from a toolbar for controlling various aspects of simulator operation. The user can open a selection of control panels and arrange them according to preference. An "update" command saves the arrangement for future WRspice sessions. Unlike Jspice3, WRspice does not contain an internal schematic capture front-end. Instead, it is designed to work in conjunction with the powerful Xic graphical editor.

WRspice includes several unique features, including a built-in Verilog parser and language extensions for mixed-mode (analog/digital) simulations, and random noise sources.

Although the command line interface remains (though it has been enhanced) many users prefer the graphical controls. The large number of "set" variables has been reduced to a few graphical buttons and input boxes.

Context sensitive help is provided throughout. The HTML-based help system functions as a web browser, making Internet resources conveniently available. The help database can be easily augmented with site-specific information.

WRspice provides internal device models through a separate library loaded at run time. This library is modifiable by the user, so that the user with some programming experience in the C++ language can add, modify, or delete device models. The user has full control over the device models used by the simulator, and can easily add specialized models needed for the user's applications.

WRspice works seamlessly with the Xic graphical editor program, providing the illusion of a single application to the user. Xic provides a graphical framework for generating input from a schematic, initiating the simulation run, and plotting output. WRspice is also highly effective as a stand-alone application, where input is supplied in ascii files using a superset of the industry standard Spice syntax.

A powerful scripting language and interpreter are provided, so that automated simulation and data manipulation can be employed. The syntax used is an efficient but easy to learn C-like scripting language representing a superset of the capabilities of the scripting language used in Spice3.

Commands exist for certain repetitive analysis types, such as Monte Carlo and operating range analysis. A "loop" command analyzes a circuit while varying circuit parameters, producing multi-dimensional output vectors. WRspice has the capability of parceling out tasks to other machines on a network, greatly reducing the time required for a multi-analysis job.

WRspice provides the following basic analysis types:

  • DC Operating Point
  • DC Sweep (two dimensions)
  • AC
  • Noise
  • Distortion
  • Transfer Function
  • Sensitivity
  • Transient
  • Operating Range
  • Monte Carlo
The ac, noise, transfer function, and transient analyses can be performed at every point of a dc sweep using the "loop" analysis mode.

WRspice includes a Verilog parser and support for "verilog blocks" embedded in circuit descriptions. This facilitates mixed-mode simulation, and instrumentation for stochastic analysis. The release package includes a stand-alone Verilog simulator.

The supplied device model library provides the following devices:

  • Bipolar Transistor
  • Capacitor
  • Junction Diode
  • Inductor and Coupled Inductors
  • JFET
  • Josephson Junction
  • Lossy Transmission Line (convolution model)
  • MESFET
  • MOSFET (see listing below)
  • Resistor
  • Switch
  • Lossless Transmission Line
  • Lumped URC Line
  • Dependent and Independent Current and Voltage Sources
A powerful graphical plotting facility is available for plotting simulation results, with hard copy support for Postscript (mono and color), HP PCL, HPGL, and others.

Whiteley Research provides bug fixes within hours to days of reporting, and limited customization and consulting for customers of WRspice. Upgrades are provided frequently over the Internet.

WRspice is available for FreeBSD, Linux, Sun Solaris (sparc), and Microsoft Windows.


WRspice provides the following MOS models (current for release 2.2.54).

Level Name Description
1 MOS The SPICE3 mos1 (Shichman-Hodges) model
2 MOS The SPICE3 mos2 model
3 MOS The SPICE3 mos3 model
4 BSIM1 The SPICE3 bsim1 model
5 BSIM2 The SPICE3 bsim2 model, successor to bsim1
6 MOS The SPICE3 mos6 model
7, 49 BSIM3.2 U.C. Berkeley bsim3.2 model
8 BSIM3.2.4 U.C. Berkeley bsim3.2.4 model http://www-device.eecs.berkeley.edu/~bsim3/latenews.html
9 B3SOI3.0 U.C. Berkeley bsim3soi-3.0 model http://www-device.eecs.berkeley.edu/~bsimsoi
10 UFS U. Florida soi model release 7.5 http://www.soi.tec.ufl.edu
14 BSIM4.2.1 U.C. Berkeley bsim4.2.1 http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
33 Soi3 Southampton Thermal Analogue SOI MOSFET (STAG) release 2.6 http://www.micro.ecs.soton.ac.uk/stag
44 EKV-2.6 PRELIMINARY EKV-2.6 MOS model from EPFL, Lausanne, Switzerland
60 HiSIM-1.1 Hiroshima University hisim-1.1 http://www.starc.or.jp/kaihatu/pdgr/hisim


Copyright © Whiteley Research Inc. 2004