Xic contains a facility for extracting a netlist from the physical database, and comparing it with the schematic in the electrical database. Xic can also recognize devices in the physical layout, extract geometric and electrical data from these devices, and correspondingly update properties of electrical device instances. The netlists extracted from the physical and electrical databases can be compared. This layout vs. schematic (LVS) testing is a useful means of minimizing mask errors.
The Extract Menu contains command buttons for performing extraction and related functions. The commands are summarized in the table below, which provides the internal command name and a brief description.
Extract Menu | |||
Label | Name | Pop-up | Function |
---|---|---|---|
Select Groups | gnsel | none | Select groups |
Quick Paths | qpath | none | Highlight conducting paths |
Show Paths | paths | none | Highlight conducting paths |
Show Groups | group | none | Show group numbers |
Show Nodes | nodes | none | Show node numbers |
Show Terminals | tshow | none | Show terminals |
Edit Terminals | tedit | none | Edit terminal names/locations |
Find Terminals | tfind | subwindow | Locate terminal |
Source SPICE | sourc | Source SPICE File | Update from SPICE file |
Source Physical | exset | Source Physical | Update electrical from physical |
Dump Phys Netlist | pnet | Dump Phys Netlist | Save physical netlist |
Dump Elec Netlist | enet | Dump Elec Netlist | Save electrical netlist |
Dump LVS | lvs | none | Save physical/electrical comparison |
Compare Devices | cmpar | none | Compare/set devices |
Compute Params | cmput | none | Compute electrical parameters |
Extract RLC | exrlc | RLC Extraction | Extract electrical parameters |
Edit Extraction | adelp | Parameter Editor | Edit extraction parameters |
There are three internal operations performed by the extraction system: grouping, extraction, and association. These operations are performed as needed, and have to be performed only once, unless the cell is modified. The technology file specifies the information necessary to perform these operations. Grouping assigns a group number to each collection of connected conducting objects. It identifies connections through vias and contact layers, and takes into account the operations specified in ``Conductor Exclude'' directives. Extraction is the identification of physical devices and subcircuits, and establishment of the connections. This is the most compute-intensive task, since connections can be made through and between subcells, the entire cell hierarchy must be processed. Extraction also provides measurement of parameter values based on geometry. Association provides the linkage to the elements of the schematic. During association, a file named associate.log is produced, which contains messages emitted during the association process.
If the extraction cannot complete due to an error, or if an important error is identified such as problems in the technology file setup, a window containing the associate.log file will appear. This will contain messages which should help identify the problem. Note that lack of association is not considered an error. It is up to the user to make sure that the electrical and physical designs are consistent, and that terminals get placed correctly.
In the present version, all device extraction is performed automatically, thus there is no need or provision for manual placement of device terminals. The connection terminals to the current cell can be placed (with the Edit Terminals command), however this is not usually necessary. Manually placing these terminals may assist in the association process, and may be needed in some cases to resolve ambiguity.
The association algorithm works by comparing electrical and physical devices, subcircuits, and nodes, finding matches by evaluating a context score. The pair with the highest unambiguous context score are taken as duals. If the matching is ambiguous, a permutation search is performed, and the permutation with the lowest number of non-resolutions is kept.
Caveat: It may not be possible to associate some topologies, in which case there is no means at present to coerce convergence. Example files that don't associate would be welcomed for debugging purposes.
Many of the devices in the device library have physical terminal extensions included in their node property definitions. These are the ``physical'' devices, such as resistors, capacitors, and transistors. Other devices, such as voltage and current sources, are not physically implementable and have the nophys property assigned. These devices have no physical terminal extensions, thus will not appear in netlists generated from the physical layout. There is a third class of ``device'' in the device library, which includes the gnd (ground) and vcc terminals. These have no explicit physical implementation, but are an implicit part of the wiring net as they assign connection indices to the net to which they are connected.
When a device is placed in the electrical schematic, a physical terminal for each device connection is associated with the physical cell. In physical mode, these terminals are made visible with the Show Terminals button. Before association, these terminals are grouped just outside of the lower left corner of the physical cell's bounding box. During association, these terminals are moved to their proper locations in the physical layout.
Xic has an algorithm for determining conductor paths due to touching objects on a layer, and through vias between layers (if the Via keyword has been included in the technology file for the via layers). This algorithm, coupled with knowledge of the contact locations provided by device and subcircuit extraction, provides the basis for the association.
In each subcircuit instance, each conductor group is extracted, transformed to parent cell coordinates, and compared with the parent conductor groups and other subcircuit conductor groups for connectivity. Connectivity between conductor groups can be established through
Any subcell whose electrical part has no connections is checked for connectivity, and used to reduce the group numbering in the parent cell. Thus, the conductor group extends through via cells, for example. Vias and similar wiring cells should have no electrical terminals, and should not be placed in the schematic.
One complexity that arises is that a device such as an inductor or transmission line is often implemented simply as a strip of conducting material. In order to insert the device, the grouping algorithm has to be fooled into thinking that the strip which is the device is actually two disconnected strips, one for each terminal. This can be accomplished with the introduction of special layers used in layout. In particular, for an inductor, three new layers are used. One layer defines the area of the inductor device. A second layer is used to identify the contacts, and a third layer is used in a ``Conductor Exclude'' directive to separate the inductor conductor into two groups.
Separate commands are available for generating netlist files from the physical and electrical data. The Dump LVS command performs the layout vs. schematic comparison, and prints errors in a file and on-screen.
In extraction there is a capability for automatically flattening certain physical subcells in the extracted netlist. The cells to be automatically flattened must have names that begin with a common prefix, such as ``$$''. The flattening is enabled by setting the variable FlattenPrefix to the prefix, e.g.,
!set FlattenPrefix $$
When a flattenable subcell is found during extraction, all devices and sub-subcells in the subcell are linked into the parent cell for extraction and LVS purposes. References to these cells will disappear from the Dump Phys Netlist and Dump LVS listings, unless the boolean variable PnetListAll is set, in which case they are listed.
In many EDA systems, extensive use is made of special cells for MOS devices, for example. These may be automatically generated or pulled from some library. In use, it is more than cumbersome to identify each such device with a subcell in the schematic. The facility above allows the user to avoid this.
The extraction subsystem requires that a number of items be set up properly in the technology file. This includes the setting of keywords in layer blocks to identify layers that serve as conductors or vias, and definition of Device blocks which allow certain devices to be recognized by their physical structure. Wire nets and subcircuit connectivity are determined automatically by assembling groups of similar objects that touch or overlap, or are connected through a via. Once conductor groups are established, devices are extracted, and device terminals are assigned a conductor group index. This results in a description of the circuit which can be compared with the electrical schematic for consistency.
The core of the extraction is an algorithm for determining conductor paths due to touching objects on a layer, and through vias between layers (if the Via keyword has been included in the technology file for the via layers). This algorithm, coupled with knowledge of the terminal locations, provides the basis for the extraction. This ``grouping'' is performed when needed, and along with related extraction functions accounts for the delay and activity noted in response to many of the command buttons and other operations. Once a cell is processed, it is not regrouped unless the cell is modified. The Show Groups button in the Extract Menu performs grouping if necessary, and displays the group numbers. Each group (conductor net) is assigned a number. While the Show Groups button is active, these numbers are printed on-screen near the conducting objects.
The extraction algorithm can handle the situation where there is a single ground plane layer, either clear or dark field. Groups connected to ground are always assigned to group number zero. Group zero is only used when a layer has been identified as a ground plane through one of the keywords.
By default, handling of a GroundPlane (clear field) layer is the same as for other Conductor layers, however, in the top-level cell, the largest area group extracted on this layer is assigned to group 0, the ground group. There an alternative mode where all areas of the layer, in any cell, are assigned to the ground group.
There are two levels of support for a dark-field ground plane, indicated by the presence or absence of the MultiNet keyword following ``GroundPlaneClear''. The simplest situation is where the MultiNet keyword is absent. In this case, terminals and contacts with no connection, which would otherwise connect to the GroundPlaneClear layer if that layer were present, are assigned to group 0 (ground).
For example, suppose the technology file contained the following lines:
Layer M0
GroundPlaneClear
...
Layer I0
Via M1 M0
In this case, an area of I0 over an area of M1 and not over an area of M0 would indicate a connection of the M1 area to ground.
To repeat, if the MultiNet keyword does not appear, then all areas outside of the GroundPlaneClear layer geometry are assumed to be above ground. Vias and Contacts that have been specified for the ground plane layer will make contact to ground in the absence of the ground plane layer.
Although this sometimes works for simple cells, it can lead to trouble. Suppose that an island of ground plane metal is used as part of the metalization for the chip pads. This would appear as a hole in the displayed representation of the ground plane layer. Then each pad will be extracted as shorted to ground!
If the MultiNet keyword is given following the GroundPlaneClear keyword, then an internal layer, which is the inverse polarity of the ground plane layer, will be created and used for extraction purposes. The algorithm used for inversion can be specified by an integer 0-2 which optionally follows ``MultiNet''. There are also !set variables which parallel the technology file keywords. Complete information can be found in the Extraction Setup topic.